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CH7013B
Chrontel CHRONTEL CHRONTEL CHRONTEL
Digital PC to TV Encoder
1. FEATURES
* Universal digital interface accepts YCrCb (CCIR601 or 656) or RGB (15, 16 or 24-bit) video data in both non-interlaced and interlaced formats * True scale rendering engine supports underscan operations for various graphics resolutions * Enhanced text sharpness and adaptive flicker removal with up to 5-lines of filtering * Enhanced dot crawl control and area reduction * Fully programmable through serial port * Supports NTSC, NTSC-J, and PAL (B, D, G, H, I, M and N) TV formats * Provides Composite, S-Video and SCART outputs * Auto-detection of TV presence * Supports VBI pass-through * Programmable power management * 9-bit video DAC outputs * Complete Windows and DOS driver software * Offered in 48-pin LQFP
2. GENERAL DESCRIPTION
Chrontel's CH7013B digital PC to TV encoder is a standalone integrated circuit providing a robust solution for TV output. It provides a universal digital input port to accept a pixel data stream from a compatible VGA controller (or equivalent) and converts it directly into the NTSC or PAL TV format. This device integrates a digital NTSC/PAL encoder with a 9bit DAC interface, an adaptive flicker filter, and a high accuracy low-jitter phase locked loop to create outstanding quality video. Through its true scale scaling and deflickering engine, the CH7013B supports full vertical and horizontal underscan capability and operates in 5 different resolutions including 640x480 and 800x600. A universal digital interface along with full programmability make the CH7013B ideal for system-level PC solutions. All features are software programmable through a serial port to enable a complete PC solution using a TV as the primary display.
LINE MEMORY
YUV-RGB CONVERTER
RGB-YUV CONVERTER DIGITAL
D[15:0] PIXEL DATA
INPUT INTERFACE
TRUE SCALE SCALING & DEFLICKERING ENGINE
NTSC/PAL ENCODER & FILTERS
Y/R TRIPLE DAC C/G CVBS/B
SYSTEM CLOCK
RSET
SERIAL CONTROL
BLOCK
PLL
TIMING & SYNC GENERATOR
CLOCK
DATA
ADDR
XCLK
H
V
XI XO/FIN CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
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3. PIN DESCRIPTIONS
3.1 Package Diagram
CH7013B
P-OUT
DGND
AGND
DVDD
XCLK
BCO
D[2]
D[1]
D[0]
48
47
46 45
44
43
42
41
40
39
38
D[3] D[4] D[5] D[6] DVDD D[7] D[8] DGND D[9] D[10] D[11] NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
37 36 35 34 33
XO/FIN XI AVDD DVDD ADDR DGND CLOCK DATA VDD RSET GND NC
NC
H
V
CHRONTEL CH7013B
32 31 30 29 28 27 26 25
16
17
18 19
20
21 22
CVBS GND
23
C
D[12]
D[13]
D[14]
D[15]
NC
CSYNC
DVDD
Figure 2: 48-PIN LQFP (7mm x 7mm)
2
DGND
Y
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3.2 Pin Descriptions
Table 1. Pin Descriptions
48-Pin LQFP
17-14, 11-9, 7-6, 4-1, 48-46
CH7013B
Type
In
Symbol
D15-D0
Description
Digital Pixel Inputs These pins accept digital pixel data streams with either 8, 12, or 16-bit multiplexed or 16-bit non-multiplexed formats, determined by the input mode setting (see Registers and Programming section). Inputs D0 - D7 are used when operating in 8bit multiplexed mode. Inputs D0 - D11 are used when operating in 12-bit mode. Inputs D0 - D15 are used when operating in 16-bit mode. The data structure and timing sequence for each mode is described in the section on Digital Input Port. Pixel Clock Output The CH7013B, operating in master mode, provides a pixel data clocking signal to the VGA controller. This pin provides the pixel clock output signal (adjustable as X, 2X or 3X) to the VGA controller (see the section on Digital Video Interface and Registers and Programming for more details). The capacitive loading on this pin should be kept to a minimum. Pixel Clock Input To operate in a pure master mode, the P-OUT signal should be connected to the XCLK input pin. To operate in a pseudo-master mode, the P-OUT clock is used as a reference frequency, and a signal locked to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input to the XCLK pin. To operate in slave mode, the CH7013B accepts an external pixel clock input at this pin. The capacitive loading on this pin should be kept to a minimum. Vertical Sync Input/Output This pin accepts the vertical sync signal from the VGA controller, or outputs a vertical sync to the VGA controller. The capacitive loading on this pin should kept to a minimum. Horizontal Sync Input/Output This pin accepts the horizontal sync from the VGA controller, or outputs a horizontal sync to the VGA controller. The capacitive loading on this pin should be kept to a minimum. Buffered Clock Output This pin provides a buffered output of the 14.31818 MHz crystal input frequency for other devices and remains active at all times (including power-down). The output can also be selected to be other frequencies (see Registers and Programming). Crystal Input A parallel resonance 14.31818 MHz ( 50 ppm) crystal should be attached between XI and XO/FIN. However, if an external CMOS clock is attached to XO/FIN, XI should be connected to ground. Crystal Output or External Fref A 14.31818 MHz ( 50 ppm) crystal may be attached between XO/FIN and XI. An external CMOS compatible clock can be connected to XO/FIN as an alternative. Reference Resistor A 300 resistor with short and wide traces should be attached between RSET and ground. No other connections should be made to this pin. Luminance Output A 75 termination resistor with short traces should be attached between Y and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the luma video signal. In SCART mode, this pin outputs the red signal. Chrominance Output A 75 termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the chroma video signal. In SCART mode, this pin outputs the green signal.
41
Out
P-OUT
43
In
XCLK
45
In/Out
V
44
In/Out
H
39
Out
BCO
35
In
XI
36
In
XO/FIN
27
In
RSET
24
Out
Y/R
23
Out
C/G
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Table 1. Pin Descriptions
48-Pin LQFP
22
CH7013B
Symbol
CVBS/B
Type
Out
Description
Composite Video Output A 75 termination resistor with short traces should be attached between CVBS and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the composite video signal. In SCART mode, this pin outputs the blue signal. Composite Sync Output A 75 termination resistor with short traces should be attached between CSYNC and ground for optimum performance. In SCART mode, this pin outputs the composite sync signal. Serial Data (External pull-up required) This pin functions as the serial data pin of the serial interface port (see the serial Port Operation section for details). Serial Clock (Internal pull-up) This pin functions as the serial clock pin of the serial interface port (see the serial Port Operation section for details). Serial Address Select (Internal pull-up) This pin is the serial Address Select pin, which corresponds to bits 1 and 0 of the serial device address, creating an serial port address selection as follows: ADDR Serial Address Selected 1 111 0101 = 75h = 117 0 111 0110 = 76h = 118 NOTE: The serial port address is not to be confused with the Device Address Byte. The Device Address Byte is composed of 8 bits rather than 7 bits where the first 7 bits is the serial port address and the last bit is the read/write bit. Please refer to AN47 for details. Analog ground These pins provide the ground reference for the analog section of the CH7013B, and MUST be connected to the system ground, to prevent latchup. Refer to the Application Information section for information on proper supply de-coupling. Analog Supply Voltage These pins supply the +3.3V power to the analog section of the CH7013B. DAC Power Supply These pins supply the +3.3V power to CH7013B's internal DAC's. DAC Ground These pins provide the ground reference for CH7013B's internal DACs. For information on proper supply de-coupling, please refer to the Application Information section. Digital Supply Voltage These pins supply the +3.3V power to the digital section of CH7013B. Digital Ground These pins provide the ground reference for the digital section of CH7013B, and MUST be connected to the system ground to prevent latchup.
19
Out
CSYNC
29
In/Out
DATA /SD CLOCK /SL ADDR
30
In
32
In
38
Power
AGND
34 28 20, 26
Power Power Power
AVDD VDD GND
5, 18, 33, 42 8, 20, 31, 40
Power Power
DVDD DGND
4
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4. DIGITAL VIDEO INTERFACE
CH7013B
The CH7013B digital video interface provides a flexible digital interface between a computer graphics controller and the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control through the CH7013B register set. This interface can be configured as 8, 12 or 16-bit inputs operating in either multiplexed mode or 16-bit input operation in de-multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit) data formats and will accept both non-interlaced and interlaced data formats. A summary of the input data format modes is as follows:
Table 2. Input Data Formats
Bus Width Transfer Mode Color Space and Depth Format Reference
16-bit 15-bit 16-bit 8-bit 8-bit 8-bit 8-bit 12-bit 12-bit 16-bit
Non-multiplexed Non-multiplexed Non-multiplexed 2X-multiplexed 2X-multiplexed 3X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed 2X-multiplexed
RGB 16-bit RGB 15-bit YCrCb (24-bit) RGB 15-bit RGB 16-bit RGB 24-bit YCrCb (24-bit) RGB 24 RGB 24 RGB 24 (32)
5-6-5 each word 5-5-5 each word CbY0,CrY1...(CCIR656 style) 5-5-5 over two bytes 5-6-5 over two bytes 8-8-8 over three bytes Cb,Y0,Cr,Y1,(CCIR656 style) 8-8-8 over two words - `C' version 8-8-8 over two words - `I' version 8-8,8X over two words
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode. The CH7013B can operate in either master (the CH7013B generates a pixel frequency which is either returned as a phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock). The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X, or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7013B will automatically use both clock edges, if a multiplexed data format is selected. Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be selected to be generated by the CH7013B. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first value of the (Total Pixels/Line x Total Lines/Frame) column of the (display Mode Register 00h description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync signal must be able to be set to the second value in the: (Total Pixels/Line x Total Lines/Frame) column of Table 17). Master Clock Mode: The CH7013B generates a clock signal (output at the P-OUT pin) which will be used by the VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity). Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the specified setup and hold times with respect to the pixel clock.
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Pixel Data: Active pixel data will be expected after a programmable number of pixels times the multiplex rate after the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus horizontal sync width, will determine when the chip will begin to sample pixels.
4.1 Non-multiplexed Mode
In the 15/16-bit mode shown in Table 3, the pixel data bus represents a 15/16-bit non-multiplexed data stream, which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb followed by Cr. The Cb and Cr data will be co-sited with the Y value transmitted with the Cb value, with the data sequence described in Table 3. The first active pixel is SAV pixels after the trailing edge of horizontal sync, where SAV is a bus-controlled register.
HSYNC tHD XCLK
tHSW tP1 SAV tSP P0 P1 tPH1
Pixel Data
tHP1 P3 P4 P5
P2
Figure 3: Non-multiplexed Data Transfers Table 3. 15/16-bit Non-multiplexed Data Formats
IDF# Format Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0 RGB 5-6-5 P0 R0[4] R0[3] R0[2] R0[1] R0[0] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0] P1 R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] 3 RGB 5-5-5 P0 x R2[4] R2[3] R2[2] R2[1] R2[0] G2[4] G2[3] G2[2] G2[1] G2[0] B2[4] B2[3] B2[2] B2[1] B2[0] P1 x R3[4] R3[3] R3[2] R3[1] R3[0] G3[4] G3[3] G3[2] G3[1] G3[0] B3[4] B3[3] B3[2] B3[1] B3[0] P0 Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] 1 YCrCb (16-bit) P1 Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] P2 Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P3 Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0]
When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data streams), and the first byte of the `video timing reference code' will be assumed to occur when a Cb sample would occur - if the video stream was continuous. This is delineated in Table 4 below.
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Table 4. YCrCb Non-multiplexed Mode with Embedded Syncs
IDF# Format
Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P1 S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] 0 0 0 0 0 0 0 0 P2 Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0]
CH7013B
1 YCrCb 16-bit
P3 Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] P4 Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P5 Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0] Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P6 Y4[7] Y4[6] Y4[5] Y4[4] Y4[3] Y4[2] Y4[1] Y4[0] Cb4[7] Cb4[6] Cb4[5] Cb4[4] Cb4[3] Cb4[2] Cb4[1] Cb4[0] P7 Y5[7] Y5[6] Y5[5] Y5[4] Y5[3] Y5[2] Y5[1] Y5[0] Cr4[7] Cr4[6] Cr4[5] Cr4[4] Cr4[3] Cr4[2] Cr4[1] Cr4[0]
In this mode, the S[7-0] byte contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3:0] are ignored.
4.2 Multiplexed Mode
Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The multiplexed input data formats are shown in Figure 4 and 5. The Pixel Data bus represents an 8, 12, or 16-bit multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8, and 9, the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values (e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples -- and the following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is dependent upon the current mode, (not 27MHz, as specified in CCIR656).
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HS tHD XCLK
DEC = 0
tHSW
tP2 tPH2
tSP2
tHP2
XCLK
DEC = 1
tSP2
tHP2
tSP2
tHP2
D[15:0]
P0a
P0b
P1a
P1b
P2a
P2b
Figure 4: Multiplexed Pixel Data Transfer Mode
Table 5.RGB 8-bit Multiplexed Mode
IDF# Format
Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0]
7 RGB 5-6-5
P0b R0[4] R0[3] R0[2] R0[1] R0[0] G0[5] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[4] R1[3] R1[2] R1[1] R1[0] G1[5] G1[4] G1[3] P0a G0[2] G0[1] G0[0] B0[4] B0[3] B0[2] B0[1] B0[0]
8 RGB 5-5-5
P0b x R0[4] R0[3] R0[2] R0[1] R0[0] G0[4] G0[3] P1a G1[2] G1[1] G1[0] B1[4] B1[3] B1[2] B1[1] B1[0] P1b x R1[4] R1[3] R1[2] R1[1] R1[0] G1[4] G1[3]
Table 6. RGB 12-bit Multiplexed Mode
IDF# Format Pixel# Bus Data D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] 4 12-bit RGB (12-12) P0b R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] P1a G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B1[1] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] G1[7] G1[6] G1[5] G1[4] P0a G0[4] G0[3] G0[2] B0[7] B0[6] B0[5] B0[4] B0[3] G0[0] B0[2] B0[1] B0[0] 5 12-bit RGB (12-12) P0b R0[7] R0[6] R0[5] R0[4] R0[3] G0[7] G0[6] G0[5] R0[2] R0[1] R0[0] G0[1] P1a G1[4] G1[3] G1[2] B1[7] B1[6] B1[5] B1[4] B1[3] G1[0] B1[2] B1[1] B1[0] P1b R1[7] R1[6] R1[5] R1[4] R1[3] G1[7] G1[6] G1[5] R1[2] R1[1] R1[0] G1[1]
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Table 7. RGB 16-bit Muliplexed Mode
IDF# Format
Pixel# Bus Data D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0]
CH7013B
2 16-bit RGB (16-8)
P0b A0[7] A0[6] A0[5] A0[4] A0[3] A0[2] A0[1] A0[0] R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] P1a G1[7] G1[6] G1[5] G1[4] G1[3] G1[2] G1[1] G1[0] B1[7] B1[6] B1[5] B1[4] B1[3] B1[2] B0[1] B0[0] P1b A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[0] R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0]
Note: The AX[7:0] data is ignored.
Table 8. YCrCb Multiplexed Mode
IDF# Format Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a Cb0[7] Cb0[6] Cb0[5] Cb0[4] Cb0[3] Cb0[2] Cb0[1] Cb0[0] P0b Y0[7] Y0[6] Y0[5] Y0[4] Y0[3] Y0[2] Y0[1] Y0[0] P1a Cr0[7] Cr0[6] Cr0[5] Cr0[4] Cr0[3] Cr0[2] Cr0[1] Cr0[0] 9 YCrCb 8-bit P1b Y1[7] Y1[6] Y1[5] Y1[4] Y1[3] Y1[2] Y1[1] Y1[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
When IDF = 9 (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the embedded sync will follow the CCIR656 convention, and the first byte of the "video timing reference code" will be assumed to occur when a Cb sample would occur if the video stream was continuous. This is delineated in Table 9 shown below.
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Table 9. YCrCb Multiplexed Mode with Embedded Syncs
IDF# Format
Pixel# Bus Data D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] P0a 1 1 1 1 1 1 1 1 P0b 0 0 0 0 0 0 0 0 P1a 0 0 0 0 0 0 0 0
CH7013B
9 YCrCb 8-bit
P1b S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] P2a Cb2[7] Cb2[6] Cb2[5] Cb2[4] Cb2[3] Cb2[2] Cb2[1] Cb2[0] P2b Y2[7] Y2[6] Y2[5] Y2[4] Y2[3] Y2[2] Y2[1] Y2[0] P3a Cr2[7] Cr2[6] Cr2[5] Cr2[4] Cr2[3] Cr2[2] Cr2[1] Cr2[0] P3b Y3[7] Y3[6] Y3[5] Y3[4] Y3[3] Y3[2] Y3[1] Y3[0]
In this mode the S[7:0] contains the following data: S[6] S[5] S[4] = = = F V H = = = 1 during field 2, 0 during field 1 1 during field blanking, 0 elsewhere 1 during EAV (the synchronization reference at the end of active video) 0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3:0] are ignored.
HSYNC POut/ XCLK Pixel D[7:0] Data tHD
tHSW tP3 tSP3 P0a P0b tPH3
tHP3 P0c P1a P1b P1c
Figure 5: Multiplexed Pixel Data Transfer Mode (IDF = 6) Table 10. RGB 8-bit Multiplexed Mode (24-bit Color)
IDF# Format Pixel# Bus Data P0a B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] P0b G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] P0c R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] 6 RGB 8-bit P1a P1b B1[7] G1[7] B1[6] G1[6] B1[5] G1[5] B1[4] G1[4] B1[3] G1[3] B1[2] G1[2] B1[1] G1[1] B1[0] G1[0] P1c R1[7] R1[6] R1[5] R1[4] R1[3] R1[2] R1[1] R1[0] P2a B2[7] B2[6] B2[5] B2[4] B2[3] B2[2] B2[1] B2[0] P2b G2[7] G2[6] G2[5] G2[4] G2[3] G2[2] G2[1] G2[0] P2c R2(7) R2(6) R2(5) R2(4) R2(3) R2(2) R2(1) R2(0)
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
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4.3 Functional Description
CH7013B
The CH7013B is a TV-output companion chip to graphics controllers providing digital output in either YUV or RGB format. This solution involves both hardware and software elements which work together to produce an optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are integrated on-chip. On-chip circuitry includes memory, memory control, scaling, PLL, DAC, filters, and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog components. No additional adjustment is required during manufacturing. CH7013B is ideal for PC motherboards, web browsers, or VGA add-in boards where a minimum of discrete support components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.
4.3.1 Architectural Overview
The CH7013B is a complete TV output subsystem which uses both hardware and software elements to produce an image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a compatible TV output from a VGA input involves a relatively straightforward process. This process includes a standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with minimal artifacts from the conversion process. As a key part of the overall system solution, the CH7013B software establishes the correct framework for the VGA input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the CH7013B software may be invoked to establish the appropriate TV output display. The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7013B can render a superior TV image without the added cost of a full frame buffer memory - normally used to implement features such as scaling and full synchronization. The CH7013B hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel clock. These inputs are then color-space converted into YUV in 4-2-2 format and stored in a line buffer memory. The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line and 5line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.
In order to minimize the hazard of ESD, a set of protection diodes MUST BE used for each DAC connecting to TV (Refer to AN-38 for details).
4.3.2 Color Burst Generation*
The CH7013B allows the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the sub-carrier frequency independent of the sampling rate. As a result, the CH7013B may be used with any VGA chip (with an appropriate digital interface) since the CH7013B sub-carrier frequency can be generated without being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a 0.01% sub-carrier frequency variation may be enough to cause some television monitors to lose color lock. In addition, the CH7013B has the capability to genlock the color burst signal to the VGA horizontal sync frequency, which enables a fully synchronous system between the graphics controller and the television. When genlocked, the CH7013B can also stop "dot crawl" motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set.
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4.3.3 Display Modes
CH7013B
The CH7013B display mode is controlled by three independent factors: input resolution, TV format, and scale factor, which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400, and 512x384. It is designed to support output to either NTSC or PAL television formats. The CH7013B provides interpolated scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which are listed in detail in Table 11.
Table 11. CH7013B Display Modes
TV Format Standard
NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL PAL
Input (active) Resolution
640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 640x400 720x400 720x400 512x384 512x384 640x480 640x480 640x480 800x600 800x600 800x600 640x400 640x400 720x400 720x400 512x384 512x384
Scale Factor
1:1 7:8 5:6 5:6 3:4 7:10 5:4 1:1 7:8 5:4 1:1 5:4 1:1 5:4 1:1 5:6 1:1 5:6 3:4 5:4 1:1 5:4 1:1 5:4 1:1
Active TV Lines
480 420 400 500 450 420 500 400 350 500 400 480 384 600 480 400 600 500 450 500 400 500 400 480 384
Percent (1) Overscan/ (underscan)
10% (3%) (8%) 16% 4% (3%) 16% (8%) (19%) 16% (8%) 10% (11%) 14% (8%) (29%) 14% (4%) (15%) (4%) (29%) (4%) (29%) (8%) (35%)
Pixel Clock
24.671 28.196 30.210 39.273 43.636 47.832 21.147 26.434 30.210 23.790 29.455 20.140 24.671 21.000 26.250 31.500 29.500 36.000 39.000 25.000 31.500 28.125 34.875 21.000 26.250
Horizontal Total
784 784 800 1040 1040 1064 840 840 840 945 936 800 784 840 840 840 944 960 936 1000 1008 1125 1116 840 840
Vertical Total
525 600 630 630 700 750 420 525 600 420 525 420 525 500 625 750 625 750 836 500 625 500 625 500 625
(1) Note: Percent overscan/(underscan) is a calculated value based on average viewable lines on each TV format, assuming an average TV overscan of 10%. (Negative values) indicate modes which are operating in underscan. For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average) For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)
The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the CH7013B for different application needs. In general, underscan (modes where percent overscan is negative) provides an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g., viewing text screens, operating games, running productivity applications and working within Windows). Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the computer. In addition to the above mode table, the CH7013B also support interlaced input modes, both in CCIR 656 and proprietary formats (see Display Mode Register section.)
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4.3.4 Flicker Filter and Text Enhancement
CH7013B
The CH7013B integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates proprietary Algorithms for enhancing the readability of text. These modes are fully programmable via the serial port under the flicker filter register.
4.3.5 Internal Voltage Reference
An on-chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference resistor at pin RSET, and register controlled divider, sets the output ranges of the DACs. The CH7013B bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal (for PAL or NTSCJ), which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor RSET is 300 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC output is 1/48th.
4.3.6 Power Management
The CH7013B supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off, and Composite Off to provide optimal power consumption for the application involved. Using the programmable power down modes accessed over the serial port, the CH7013B may be placed in either Normal state, or any of the four power managed states, as listed below (see "Power Management Register" under the Register Descriptions section for programming information). To support power management, a TV sensing function (see "Connection Detect Register" under the Register Descriptions section) is provided, which identifies whether a TV is connected to either S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).
Table 12.Power Management
Operating State
Normal (On): Power Down:
Functional Description
In the normal operating state, all functions and pins are active In the power-down state, most pins and circuitry are disabled.The BCO pin will continue to provide either the VCO divided by K3, or 14.318 MHz out, and the P-OUT pin will continue to output a clock reference. Power is shut off to the unused DACs associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the serial port circuits are disabled. This places the CH7013B in its lowest power consumption mode.
S-Video Off: Composite Off: Full Power Down:
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4.4 Luminance and Chrominance Filter Options
CH7013B
The CH7013B contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and SVideo outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown, the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and chrominance video bandwidth output is shown in Table 13.
VBI Pass-Through Support
The CH7013B provides the ability to pass-through data with minimal filtering, on vertical blanking lines 10-21 for Intercast or close captioned applications (see register descriptions).
Table 13. Video Bandwidth
Mode
00 0.62 0.78 0.53 0.65 0.83 1.03 0.70 0.87 0.74 0.93 0.63 0.78 0.89 0.62 0.78 0.93 0.64 0.74 0.79 0.77 0.95 1.02 0.77 0.86 0.94 0.71 0.71 0.47 0.38
Chrominance
Bandwidth (MHz) CBW[1:0] 01 10 0.68 0.80 0.85 1.00 0.58 0.68 0.71 0.83 0.91 1.07 1.13 1.32 0.77 0.90 0.95 1.12 0.81 0.95 1.02 1.20 0.68 0.80 0.86 1.00 0.98 1.15 0.68 0.80 0.85 1.00 1.02 1.20 0.71 0.83 0.81 0.95 0.87 1.02 0.85 1.00 1.03 1.22 1.12 1.32 0.85 0.99 0.94 1.11 1.03 1.21 0.78 0.91 0.78 0.91 0.51 0.60 0.41 0.48 11 0.95 1.18 0.81 0.99 1.27 1.57 1.07 1.33 1.13 1.42 0.95 1.19 1.36 0.95 1.18 1.42 0.98 1.13 1.21 1.18 1.44 1.56 1.18 1.31 1.44 1.08 1.08 0.71 0.57
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Luminance Bandwidth with Sin(X) /X (MHz) CVBS S-Video S-Video YCV YSV[1:0], YPEAK = 0 YSV[1:0], YPEAK = 1 00 01 1X 00 01 1X 0 1 2.26 3.37 2.26 3.37 5.23 2.57 4.44 5.23 2.82 4.21 2.82 4.21 6.53 3.21 5.56 6.53 1.93 2.87 1.93 2.87 4.46 2.19 3.79 4.46 2.36 3.52 2.36 3.52 5.46 2.68 4.64 5.46 3.03 4.51 3.03 4.51 7.00 3.44 5.95 7.00 3.75 5.59 3.75 5.59 8.68 4.27 7.38 8.68 2.56 3.81 2.56 3.81 5.92 2.91 5.04 5.92 3.17 4.72 3.17 4.72 7.33 3.60 6.23 7.33 2.69 4.01 2.69 4.01 6.22 3.06 5.29 6.22 3.39 5.05 3.39 5.05 7.84 3.85 6.67 7.84 2.28 3.39 2.28 3.39 5.26 2.59 4.48 5.26 2.84 4.24 2.84 4.24 6.58 3.23 5.59 6.58 3.25 4.84 3.25 4.84 7.52 3.70 6.39 7.52 2.26 3.37 2.26 3.37 5.23 2.57 4.44 5.23 2.82 4.21 2.82 4.21 6.53 3.21 5.56 6.53 3.39 5.05 3.39 5.05 7.84 3.85 6.67 7.84 2.35 3.50 2.35 3.50 5.43 2.67 4.62 5.43 2.70 4.02 2.70 4.02 6.24 3.07 5.30 6.24 2.89 4.31 2.89 4.31 6.68 3.29 5.68 6.68 2.82 4.20 2.82 4.20 6.53 3.21 5.55 6.53 3.44 5.13 3.44 5.13 7.97 3.92 6.77 7.97 3.73 5.56 3.73 5.56 8.63 4.24 7.34 8.63 2.82 4.20 2.82 4.20 6.52 3.20 5.54 6.52 3.13 4.66 3.13 4.66 7.24 3.56 6.16 7.24 3.43 5.11 3.43 5.11 7.94 3.90 6.75 7.94 2.58 3.85 2.58 3.85 5.97 2.94 5.08 5.97 2.58 3.85 2.58 3.85 5.97 2.94 5.08 5.97 1.70 2.53 1.70 2.53 3.92 1.93 3.34 3.92 1.37 2.04 1.37 2.04 3.17 1.56 2.69 3.17
The composite luminance and chrominance frequency response is depicted in Figure 6 through 8.
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Luminance and Chrominance Filter Options (continued)
0 0
CH7013B
-66
12 -12
-18 18
(YCVdB
YCVdB < i > n n

)
-24 24 -30 30 -36 36 -42 42 0 0
1
1
2
2
3
3
4
4
6 55 f 6 n,i f n , i
7
7
8
8
9
9
10
10
11
11
12
12
10
6
10 6
Figure 6: Composite Luminance Frequency Response (YCV = 0)
0 -6 -12
YSVdB
-18 -24 -30 -36 -42 0
(YSVdB)n
1
2
3
4
5
f n,i 10 6
6
7
8
9
10
11
12
Figure 7: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)
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Luminance and Chrominance Filter Options (continued)
CH7013B
0
-6
-12
UVfirdB n -18
(UVfirdB)n
-24
-30
-36
-42 0
1
2
3
4
5
f fn,i n , i 6 10 106
6
7
8
9
10
11
12
Figure 8: Chrominance Frequency Response
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4.5 NTSC and PAL Operation
CH7013B
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to characterize these outputs are listed in Table 14 and shown in Figure 9. (See Figures 12 through 17 for illustrations of composite and S-Video output waveforms.)
4.5.1 CCIR624-3 Compliance
The CH7013B is predominantly compliant with the recommendations called out in CCIR624-3. The following are the only exceptions to this compliance: * The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or pseudo-master modes, not in slave mode when the graphics device generates these frequencies. * It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color reference signals. * All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21, which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625). * Chroma signal frequency response will fall within 10% of the exact recommended value. * Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies used to support multiple operating modes
Table 14. NTSC/PAL Composite Output Timing Parameters (in S)
Symbol Description NTSC
A B C D E F G H Front Porch Horizontal Sync Breezeway Color Burst Back Porch Black Active Video Black 287 0 287 287 287 340 340 340
Level (mV)
PAL
300 0 300 300 300 300 300 300
Duration (uS)
NTSC
1.49 - 1.51 4.69 - 4.72 0.59 - 0.61 2.50 - 2.53 1.55 - 1.61 0.00 - 7.50 37.66 - 52.67 0.00 - 7.50
PAL
1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67
For this table and all subsequent figures, key values are:
Note: 1. 2. 3. 4. RSET = 300 ohms; V(RSET) = 1.108 V; 75 ohms doubly terminated load. Durations vary slightly in different modes due to the different clock frequencies used. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes. Black times (F and H) vary with position controls.
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CH7013B
A
B
C
DEF
G
H
Figure 9: NTSC / PAL Composite Output
STAR S TART T OF O F VSY C V NC SYN
A ALOG N G StartAN of ALO fieldFIELD 1 1 LD 1 FIE
523 520 520
524 521 521
525 522 522
1 523 523
2 524 524
3 525 525
4 1 1
5 2 2
36 3
7 4 4
58 5
9 6 6
10 7 7
11 8 8
12 9 9
Pre-equalizing pulse interval ReferenceG AN A ALO phase NALO sub-carrierG FIELD 1 FIE LD 2 color field 2 t1+V
Vertical sync pulse interval Line vertical interval
Post-equalizing pulse interval
261 258 258
262 259 259
260 260
263
264 261 261 Start of field 2
265 262 262
266 263 263
267 264 264
268 265 265
269 266 266
270 267 267
271 268 268
272 269 269
273 270 270
274 271 271
275 272 272
Reference A ALO N G sub-carrier phase FIE LD 1 t2+V color field 2
S TAR T O F VN SY C
523 520
524 521
525 522
1 523 Start of field 3
2 524
3 525
4 1
5 2
6 3
7 4
8 5
9 6
10 7
11 8
12 9
Reference G A ALO N sub-carrier phase FIE LD color field 3 2 t3+V
261 258
262 259
263 260
264 261 Start of field 4
265 262
266 263
267 264
268 265
269 266
270 267
271 268
272 269
273 270
274 271
275 272
Reference sub-carrier phase color field 4
Figure 10: Interlaced NTSC Video Timing
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STA T TR S ART O F VSY C SN Y
CH7013B
A ALO N G FIE LD 1
620 620
621 621
622 622
6 23 623
624
625
1
2
3
4
5
6
7 7
8 8
9 9
10 10
A ALO N G FIE LD 2
308 308
309 309
310 310
31 1 311
312
313
314
315
316
317
318
319 319
320 320
321 321
322 322
323 323
A ALO N G FIE LD 3
620 620
621 621
622 622
623 6 23
624
625
1
2
3
4
5
6
7 7
8 8
9 9
10 10
A ALO N G FIE LD 4
308 308
309 309
310 310
311 31 1
312
313
314
315
316
317
318
319 319
320 320
321 321
322 322
323 323
B RST BU S UR T B NK G BLA KIN LAN ING INTERVALS
4 3 E TIVE TO U B RST P AS = R FE E C P A US R HE E RNE H EFE NC PH SE = 135 R LA TO P L SW C = 0, +V C M O E T AL SW H = 0, + C M O E IT H V O P N2NT O P NN P A ITC 1 B RST P ASE = R E R NC R N E HA BU S PH E = R FE E C P A + 90 = 225 RE TIVE TO U UR T HAS EFE E E PH SE + 90 = 22 R LATIV TO U SE 5 ELA E P L SW H = 1, - V C M O E T IT O P NN PAL SW C = 1, - V C M O E T A ITCH O P NN
Figure 11: Interlaced PAL Video Timing
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CH7013B
Black Blue Red Magenta
Green Cyan Yellow
White
Color/Level White Yellow Cyan Green Magenta Red Blue Black Blank
mA 26.66 24.66 21.37 19.37 16.22 14.22 11.08 9.08 7.65
V 1.000 0.925 0.801 0.726 0.608 0.533 0.415 0.340 0.287
Color bars:
Sync
0.00
0.000
Figure 12: NTSC Y (Luminance) Output Waveform (DACG = 0)
Blue Red Magenta
Green Cyan Yellow
White
Black
Color/Level White Yellow Cyan Green Magenta Red Blue Blank/ Black
mA 26.75 24.62 21.11 18.98 15.62 13.49 10.14 8.00
V 1.003 0.923 0.792 0.712 0.586 0.506 0.380 0.300
Color bars:
Sync
0.00
0.000
Figure 13: PAL Y (Luminance) Video Output Waveform (DACG = 1)
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CH7013B
Magenta
Yellow
Green
White
Black
Cyan
Color bars:
Color/Level Cyan/Red Green/Magenta Yellow/Blue mA 25.80 25.01 22.44 V 0.968 0.938 0.842
Blue
Red
Peak Burst Blank Peak Burst
18.08 14.29 10.51
0.678 0.536 0.394
3.579545 MHz Color Burst (9 cycles)
Yellow/Blue
6.15
0.230
Green/Magenta Cyan/Red
3.57 2.79
0.134 0.105
Figure 14: NTSC C (Chrominance) Video Output Waveform (DACG = 0)
Magenta
Yellow
Green
White
Black
Cyan
Color bars:
Color/Level Cyan/Red Green/Magenta Yellow/Blue mA 27.51 26.68 23.93 V 1.032 1.000 0.897
Blue
Red
Peak Burst Blank Peak Burst
19.21 15.24 11.28
0.720 0.572 0.423
4.433619 MHz Color Burst (10 cycles)
Yellow/Blue
6.56
0.246
Green/Magenta Cyan/Red
3.81 2.97
0.143 0.111
Figure 15: PAL C (Chrominance) Video Output Waveform (DACG = 1)
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CH7013B
Magenta
Yellow
Green
White
Black
Cyan
Blue
Red
Color/Level Peak Chrome White
mA 32.88 26.66
V 1.233 1.000
Color bars:
Peak Burst Black Blank
11.44 9.08 7.65
0.429 0.340 0.287
Peak Burst
4.45
0.167
3.579545 MHz Color Burst (9 cycles)
Sync 0.00 0.000
Figure 16: Composite NTSC Video Output Waveform (DACG = 0)
Magenta
Yellow
Green
White
Black
Cyan
Blue
Red
Color/Level
mA
V 1.249 1.003
Color bars:
Peak Chrome 33.31 White 26.75
Peak Burst
11.97
0.449
Blank/Black
8.00
0.300
Peak Burst Sync
4.04 0.00
0.151 0.000
4.433619 MHz Color Burst (10 cycles)
Figure 17: Composite PAL Video Output Waveform (DACG = 1)
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5. REGISTERS AND PROGRAMMING
CH7013B
The CH7013B is a fully programmable device, providing for full functional control through a set of registers accessed from the serial port. The CH7013B contains a total of 37 registers, which are listed in Table 15 and described in detail under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previous section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter contains more than 8 bits, and the remaining bits are located in another register.
Table 15. Register Map
Register
Display Mode Flicker Filter Video Bandwidth Input Data Format Clock Mode Start Active Video Position Overflow Black Level Horizontal Position Vertical Position Sync Polarity Power Management Connection Detect Contrast Enhancement PLL M and N extra bits PLL-M Value PLL-N Value Buffered Clock Subcarrier Frequency Adjust PLL and Memory Control CIV Control Calculated Fsc Increment Value Version ID Test Address
Symbol
DMR FFR VBW IDF CM SAV PO BLR HPR VPR SPR PMR CDR CE MNE PLLM PLLN BCO FSCI PLLC CIVC CIV VID TR AR
Address
00h 01h 03h 04h 06h 07h 08h 09h 0Ah 0Bh 0Dh 0Eh 10h 11h 13h 14h 15h 17h 18h -1Fh 20h 21h 22h - 24h 25h 26h - 29h 3Fh
Bits
8 6 7 7 8 8+ 3 8 8+ 8+ 4 5 4 3 5 8+ 8+ 6 4 or 8 each 6 5 8 each 8 30 6
Functional Summary
Display mode selection Flicker filter mode selection Luma and chroma filter bandwidth selection Data format and bit-width selections Sets the clock mode to be used Active video delay setting MSB bits of position values Black level adjustment input latch clock edge select Enables horizontal movement of displayed image on TV Enables vertical movement of displayed image on TV Determines the horizontal and vertical sync polarity Enables power saving modes Detection of TV presence Contrast enhancement setting Contains the MSB bits for the M and N PLL values Sets the PLL M value - bits (7:0) Sets the PLL N value - bits (7:0) Determines the clock output at pin 41 Determines the subcarrier frequency Controls for the PLL and memory sections Control of CIV value Readable register containing the calculated subcarrier increment value Device version number Reserved for test (details not included herein) Current register being addressed
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5.1 Register Descriptions
CH7013B
Table 16. Alternate Register Map (Note: MacrovisionTM controls available only by special arrangement)
Register
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 3Fh YLM7 CLM7 Reserved YLM6 CLM6 Reserved CIV23 CIV15 CIV7 VID7 TS3 CIV22 CIV14 CIV6 VID6 TS2 CIV21 CIV13 CIV5 VID5 TS1 MS2 YLM5 CLM5 AR5 PLLCPl PLLCAP CIV25 CIV20 CIV12 CIV4 VID4 TS0 MS1 YLM4 CLM4 AR4 SHF2 SHF1 SHF0 FSCI31 FSCI27 FSCI23 FSCI19 FSCI15 FSCI11 FSCI7 FSCI3 PLLS CIV24 CIV19 CIV11 CIV3 VID3 RSA MSO YLM3 CLM3 AR3 SCO2 FSCI30 FSCI26 FSCI22 FSCl18 FSCl14 FSCl10 FSCI6 FSCI2 PLL5VD ClVH1 CIV18 CIV10 CIV2 VID2 BST MTD YLM2 CLM2 AR2 SCO1 FSCI29 FSCI25 FSCI21 FSCl17 FSCl13 FSCl9 FSCI5 FSCI1 PLL5VA ClVH0 CIV17 CIV9 CIV1 VID1 NST YLM8 YLM1 CLM1 AR1 SCO0 FSCI28 FSCI24 FSCI20 FSCl16 FSCI12 FSCI8 FSCI4 FSCI0 MEM5V AClV CIV16 CIV8 CIVO VID0 TE CLM8 YLM0 CLM0 AR0 M7 N7 M6 N6 M5 N5 Reserved M4 N4 Reserved M3 N3 N9 M2 N2 N8 M1 N1 M8 M0 N0 YT CT CE2 CVBST CE1 SENSE CE0 SCART DES Reset* SYO PD2 VSP PD1 HSP PD0 BL7 HP7 VP7 BL6 HP6 VP6 BL5 HP5 VP5 BL4 HP4 VP4 BL3 HP3 VP3 CFRB SAV7 M/S* SAV6 Reserved SAV5 MCP SAV4 XCM1 SAV3 XCM0 SAV2 SAV8 BL2 HP2 VP2 PCM1 SAV1 HP8 BL1 HP1 VP1 PCM0 SAV0 VP8 BL0 HP0 VP0 FLFF CVBW DACG CBW1 RGBBP CBW0 YPEAK IDF3 YSV1 IDF2 YSV0 IDF1 YCV IDF0
Bit 7
IR2
Bit 6
IR1
Bit 5
IRO FC1
Bit 4
VOS1 FC0
Bit 3
VOS0 FY1
Bit 2
SR2 FY0
Bit 1
SR1 FT1
Bit 0
SR0 FT0
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Display Mode Register
CH7013B
Symbol: DMR Address: 00h Bits: 8
6
IR1 R/W 1
Bit: Symbol: Type: Default:
7
IR2 R/W 0
5
IR0 R/W 1
4
VOS1 R/W 0
3
VOS0 R/W 1
2
SR2 R/W 0
1
SR1 R/W 1
0
SR0 R/W 0
This register provides programmable control of the CH7013B display mode, including input resolution (IR[2:0]), output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the table below (default is 640x480 input, NTSC output, 7/8's scaling).
Table 17. Display Modes
VOS [1:0]
00 00 01 01 00 00 01 01 00 00 01 01 01 00 00 00 01 01 01 00 00 00 01 01 01 00 01 00 01
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25* 26* 27* 28*
IR[20:]
000 000 000 000 001 001 001 001 010 010 010 010 010 011 011 011 011 011 011 100 100 100 100 100 100 101 101 110 110
SR [2:0]
000 001 000 001 000 001 000 001 010 001 000 001 010 000 001 011 001 010 011 001 011 100 011 100 101 001 001 001 001
Input Data Format (Active Video)
512x384 512x384 512x384 512x384 720X400 720x400 720x400 720x400 640x400 640x400 640x400 640x400 640x400 640x480 640x480 640x480 640x480 640x480 640x480 800x600 800x600 800x600 800x600 800x600 800x600 720x576 720x480 800x500 640X400
Total Pixels/Line x Total Lines/Frame
840x500 840x625 800x420 784x525 1125X500 1116x625 945x420 936x525 1000x500 1008x625 840x420 840x525 840x600 840x500 840x625 840x750 784x525 784x600 800x630 944x625 960x750 936x836 1040x630 1040x700 1064x750 864x625 858x525 1135x625 910X525
Output Format
PAL PAL NTSC NTSC PAL PAL NTSC NTSC PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL NTSC PAL NTSC
Scaling
5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 5/4 1/1 7/8 5/4 1/1 5/6 1/1 7/8 5/6 1/1 5/6 3/4 5/6 3/4 7/10 1/1 1/1 1/1 1/1
Pixel Clock (MHz)
21.000000 26.250000 20.139860 24.671329 28.125000 34.875000 23.790210 29.454545 25.000000 31.5000000 21.146853 26.433566 30.209790 21.000000 26.250000 31.5000000 24.671329 28.195804 30.209790 29.500000 36.0000000 39.000000 39.272727 43.636364 47.832168 13.500000 13.500000 17.734375 14.318182
* Interlaced modes of operation. (For those modes, some functions will be bypassed. For details, please contact Chrontel Application department.)
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VOS[1:0] Output Format
00 PAL 01 NTSC 10 PAL-M 11
CH7013B
NTSC-J
Flicker Filter Register
Symbol: FFR Address: 01h Bits: 6
6
Reserved R/W 0
Bit: Symbol: Type: Default:
7
Reserved R/W 1
5
FC1 R/W 1
4
FC0 R/W 1
3
FY1 R/W 0
2
FY0 R/W 0
1
FT1 R/W 1
0
FT0 R/W 0
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register 01h, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register 01h, FY [1:0] is bits 1:0 and FT[1:0] is bits 3:2.
Table 18.Flicker Filter Settings
FY[1:0] 00 01 10 11 FT[1:0] 00 01 10 11 FC[1:0] 00 01 10 11 Settings for Luma Channel Minimal Flicker Filtering Slight Flicker Filtering Maximum Flicker Filtering Invalid Settings for Text Enhancement Circuit Maximum Text Enhancement Slight Text Enhancement Minimum Text Enhancement Invalid Settings for Chroma Channel Minimal Flicker Filtering Slight Flicker Filtering Maximum Flicker Filtering Enable Chroma DotCrawl Reduction
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Reserved Register
CH7013B
Symbol: Address: 02h Bits: 8
6
Reserved R/W 0
Bit: Symbol: Type: Default:
7
Reserved R/W 0
5
Reserved R/W 0
4
Reserved R/W 0
3
Reserved R/W 1
2
Reserved R/W 0
1
Reserved R/W 1
0
Reserved R/W 1
Video Bandwidth Register
Symbol: VBW Address: 03h Bits: 8
5
CBW1 R/W 0
Bit: Symbol: Type: Default:
7
FLFF R/W 0
6
CVBW R/W 0
4
CBW0 R/W 0
3
YPEAK R/W 0
2
YSV1 R/W 0
1
YSV0 R/W 0
0
YCV R/W 0
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently four filter options defined for the chroma channel, 4 filter options in the S-Video luma channel and two filter options in the composite luma channel. The Table 19 and Table 20 below show the various settings.
Table 19. Luma Filter Bandwidth
YCV
0 1 YSV[1:0] 00 01 10 11 YPEAK 0 1
Luma Composite Video Filter Adjust
Low bandwidth High bandwidth Luma S-Video Filter Adjust Low bandwidth Medium bandwidth High bandwidth Reserved (decode this and handle the same as 10) Disables the Y-peaking circuit Disables the peaking filter in luma S-Video channel Enables the peaking filter in luma S-Video channel
Table 20. Chroma Filter Bandwidth
CBW[1:0]
00 01 10 11
Luma Composite Video Filter Adjust
Low bandwidth Medium bandwidth Med-high bandwidth High bandwidth
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A "1" in this location enables the output of a black and white image on composite, thereby eliminating the degrading effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy. Bit 7 (FLFF) controls the flicker filter used in the 7/10's scaling modes. In these scaling modes, setting FLFF to 1 causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.
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Input Data Format Register
CH7013B
Symbol: IDF Address: 04h Bits: 6
5
RGBBP R/W 0
Bit: Symbol: Type: Default:
7
Reserved Reserved 0
6
R/W R/W 0
4
Reserved Reserved 0
3
IDF3 R/W 0
2
IDF2 R/W 0
1
IDF1 R/W 0
0
IDF0 R/W 0
This register sets the variables required to define the incoming pixel data stream.
Table 21. Input Data Format
IDF[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001-1111
Description
16-bit non-multiplexed RGB (16-bit color, 565) input 16-bit non-multiplexed YCrCb (24-bit color) input (Y non-multiplexed, CrCb multiplexed 16-bit multiplexed RGB (24-bit color) input 15-bit non-multiplexed RGB (15-bit color, 555) input 12-bit multiplexed RGB (24-bit color) input ("C" multiplex scheme) 12-bit multiplexed RGB2 (24-bit color) input ("I" multiplex scheme) 8-bit multiplexed RGB (24-bit color, 888) input 8-bit multiplexed RGB (16-bit color, 565) input 8-bit multiplexed RGB (15-bit color, 555) input 8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
RGBBP (bit 5): Setting this bit enables the RGB pass-through mode. Setting this bit to a 1 causes the input RGB signal to be directly output at the DACs (subject to a pipeline delay). If RGBBP=0, the bypass mode is disabled. DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71 A, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76A, which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Symbol: CM Address: 06h Bits: 8
6
M/S* R/W 0
Bit: Symbol: Type: Default:
7
CFRB R/W 0
5
Reserved R/W 0
4
MCP R/W 1
3
XCM1 R/W 0
2
XCM0 R/W 0
1
PCM1 R/W 0
0
PCM0 R/W 0
The setting of the clock mode bits determines the clocking mechanism used in the CH7013B. The clock modes are shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the XCLK input clock.
Note: For what was formerly defined as the master mode, the user must now externally connect the P-OUT clock to the XCLK input pin. Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the input of the device. Refer to the "Input Data Format Register" for these combinations.
Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK. Display modes 27and 28 must use a 1X XCLK input data format
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Table 22. Input Data Format Register
XCM[1:0] 00
00 00 01 01 01 1X 1X 1X
CH7013B
PCM[1:0] 00
01 1X 00 01 1X 00 01 1X
XCLK 1X
1X 1X 2X 2X 2X 3X 3X 3X
P-OUT 1X
2X 3X 1X 2X 3X 1X 2X 3X
Input Data Modes Supported 0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9 0, 1, 2, 3, 4, 5, 7, 8, 9 2, 4, 5, 7, 8, 9 2, 4, 5, 7, 8, 9 2, 4, 5, 7, 8, 9 6 6 6
Note:
The Clock Mode Register also contains the following bits:
* * * MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the negative edge, one selects the positive edge. M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the 14.31818MHz clock is used as a frequency reference to the PLL . In slave mode (0) the XCLK input is used as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced to one. CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the subcarrier to free-run, and should be used when the ACIV bit is set to one.
Start Active Video Register
Symbol: SAV Address: 07h Bits: 8
5
SAV5 R/W 0
Bit: Symbol: Type: Default:
7
SAV7 R/W 0
6
SAV6 R/W 0
4
SAV4 R/W 0
3
SAV3 R/W 0
2
SAV2 R/W 0
1
SAV1 R/W 0
0
SAV0 R/W 0
This register sets the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge of sync to the first active data must be a multiple of three clocks.
Position Overflow Register
Symbol: PO Address: 08h Bits: 3
5
Reserved R/W 1
Bit: Symbol: Type: Default:
7
Reserved R/W 0
6
Reserved R/W 0
4
Reserved R/W 1
3
Reserved R/W 0
2
SAV8 R/W 0
1
HP8 R/W 0
0
VP8 R/W 0
This position overflow register contains the MSB values for the SAV, HP, and VP values, as follows:
* * * VP8 (bit 0) is the MSB of the vertical position value (see explanation under "Vertical Position Register"). HP8 (bit 1) is the MSB of the horizontal position value (see explanation under "Horizontal Position Register"). SAV8 (bit 2) is the MSB of the start of active video value (see explanation under "Start Active Video Register"). Rev. 1.2, 9/1/2004 29
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Black Level Register
CH7013B
Symbol: BLR Address: 09h Bits: 8
6
BL6 R/W 1
Bit: Symbol: Type: Default:
7
BL7 R/W 0
5
BL5 R/W 1
4
BL4 R/W 1
3
BL3 R/W 1
2
BL2 R/W 1
1
BL1 R/W 1
0
BL0 R/W 1
This register sets the black level. The luminance data is added to this black level, which must be set between 90 and 208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100 for NTSC-J. This value must be set to zero when in SCART mode.
Horizontal Position Register
Symbol: HPR Address: 0Ah Bits: 8
5
HP5 R/W 0
Bit: Symbol: Type: Default:
7
HP7 R/W 0
6
HP6 R/W 0
4
HP4 R/W 1
3
HP3 R/W 0
2
HP2 R/W 0
1
HP1 R/W 0
0
HP0 R/W 0
The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0] plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the image position by 4 input pixels.
Vertical Position Register
Symbol: VPR Address: 0Bh Bits: 8
5
VP5 R/W 0
Bit: Symbol: Type: Default:
7
VP7 R/W 0
6
VP6 R/W 0
4
VP4 R/W 0
3
VP3 R/W 0
2
VP2 R/W 0
1
VP1 R/W 0
0
VP0 R/W 0
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically centered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync) used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses). Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen. Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When panning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
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Sync Polarity Register
CH7013B
Symbol: SPR Address: 0Dh Bits: 4
6
Reserved R/W 1
Bit: Symbol: Type: Default:
7
Reserved R/W 0
5
Reserved R/W 1
4
Reserved R/W 0
3
DES R/W 0
2
SYO R/W 0
1
VSP R/W 0
0
HSP R/W 0
This register provides selection of the synchronization signal input to, or output from, the CH7013B. * HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low, and a value of one means the horizontal sync is active high. * VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low, and a value of one means the vertical sync is active high. * SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7013B. A value of one means that H and V sync are output from the CH7013B. * DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical sync will use a fixed pulse width of 2 lines.
Power Management Register
Symbol: PMR Address: 0Eh Bits: 5
5
Reserved R/W 0
Bit: Symbol: Type: Default:
7
Reserved R/W 0
6
Reserved R/W 1
4
SCART R/W 0
3
Reset* R/W 1
2
PD2 R/W 0
1
PD1 R/W 1
0
PD0 R/W 1
This register provides control of the power management functions, a software reset (Reset*) and the SCART output enable. The CH7013B provides programmable control of its operating states, as described in the table below.
Table 23. Power Management
PD[2:0]
000 001 010 011 1XX
Operating State
Composite Off Power Down S-Video Off Normal (On) Full Power Down
Functional Description
CVBS DAC is powered down Most pins and circuitry are disabled (except for the buffered clock outputs which are limited to the 14MHz output and VCO divided outputs). S-Video DACs are powered down All circuits and pins are active. All circuitry is powered down, except serial port
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself and the serial port. SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7013B will operate normally, outputting Y/C and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description sections.
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Connection Detect Register
CH7013B
Symbol: CDR Address: 10h Bits: 4
5
Reserved R/W 1
Bit: Symbol: Type: Default:
7
Reserved R/W 1
6
Reserved R/W 1
4
Reserved R/W 1
3
YT R
2
CT R
1
CVBST R
0
SENSE W 0
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs) and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register Bits 2-0 are set to 011 (normal mode). 2. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted. 3. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold value, it is considered connected, if it is above this voltage it is considered unconnected. During this step, each of the three status bits corresponding to individual analog outputs will be set if they are NOT connected. 4. Read the status bits. The status bits, Y, C, and CVBST (corresponding to S-Video Y and C outputs and composite video) now contain valid information which can be read to determine which outputs are connected to a TV. Again, a "0" indicates a valid connection, a "1" indicates an unconnected output.
Contrast Enhancement Register
Symbol: CE Address: 11h Bits: 3
5
Reserved R/W 0
Bit: Symbol: Type: Default:
7
Reserved R/W 1
6
Reserved R/W 1
4
Reserved R/W 0
3
Reserved R/W 1
2
CE2 R/W 0
1
CE1 R/W 1
0
CE0 R/W 1
This register provides control of the contrast enhancement feature of the CH7013B, according to the table below. At a setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of 011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with increasing settings of CE[2:0].
Table 24. Contrast Enhancement Function
CE[2:0]
000 001 010 011 100 101 110 111
Description (all gains limited to 0-255)
Contrast enhancement gain 3 Yout = (5/4)*(Yin-102) = Enhances Black Contrast enhancement gain 2 Yout = (9/8)*(Yin-57) Contrast enhancement gain 1 Yout = (17/16)*(Yin-30) Normal mode Yout = (1/1)*(Yin-0) = Normal Contrast Contrast enhancement gain 1 Yout = (17/16)*(Yin-0) Contrast enhancement gain 2 Yout = (9/8)*(Yin-0) Contrast enhancement gain 3 Yout = (5/4)*(Yin-0) Contrast enhancement gain 4 Yout = (3/2)*(Yin-0) = Enhances White
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256 224 192 160 128 96 64 32 0 0 32 64 96 128 160 192 224 256
CH7013B
Figure 18: Luma Transfer Function at different contrast enhancement settings
PLL Overflow Register
Symbol: MNE Address: 13h Bits: 5
5
Reserved R/W 0
Bit: Symbol: Type: Default:
7
Reserved R/W 0
6
Reserved R/W 1
4
Reserved R/W 0
3
Reserved R/W 0
2
N9 R/W 0
1
N8 R/W 0
0
M8 R/W 0
The PLL Overflow Register contains the MSB bits for the `M' and `N' vlaues, which will be described in the PLLM and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM Address: 14h Bits: 8
6
M6 R/W 1
Bit: Symbol: Type: Default:
7
M7 R/W 0
5
M5 R/W 0
4
M4 R/W 0
3
M3 R/W 0
2
M2 R/W 0
1
M1 R/W 0
0
M0 R/W 1
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to the PLL phase detector when the CH7013B is operating in master or pseudo-master clock mode. In slave mode, an external pixel clock is used instead of the frequency reference, and the division factor is determined by the XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.
PLL N Value Register
Symbol: PLLN Address: 15h Bits: 8
6
N6 R/W 0
Bit: Symbol: Type: Default:
7
N7 R/W 1
5
N5 R/W 0
4
N4 R/W 0
3
N3 R/W 0
2
N2 R/W 0
1
N1 R/W 0
0
N0 R/W 0
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CH7013B
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase detector, when the CH7013B is operating in master or pseudo-master mode. In slave mode, the value of `N' is always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master and pseudomaster modes is calculated according to the equation below:
Fpixel = Fref* [(N+2) / (M+2)] When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table below.
Table 25. M and N Values for Each Mode
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
VGA Resolution, TV Standard, Scaling Ratio
512x384, PAL, 5:4 512x384, PAL, 1:1 512X384, NTSC, 5:4 512X384, NTSC, 1:1 720X400, PAL, 5:4 720X400, PAL, 1:1 720X400, NTSC, 5:4 720X400, NTSC, 1:1 640X400, PAL, 5:4 640X400, PAL, 1:1 640X400, NTSC, 5:4 640x400, NTSC, 1:1 640X400, NTSC, 7:8 640X480, PAL, 5:4 640X480, PAL, 1:1
N 10bits
20 9 126 110 53 339 106 70 108 9 94 22 190 20 9
M 9bits
13 4 89 63 26 138 63 33 61 3 63 11 89 13 4
Mode
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VGA Resolution, TV Standard, Scaling Ratio
640X480, PAL, 5:6 640X480, NTSC, 1:1 640X480, NTSC, 7:8 640X480, NTSC, 5:6 800X600, PAL, 1:1 800X600, PAL, 5:6 800X600, PAL, 3:4 800X600, NTSC, 5:6 800X600, NTSC, 3:4 800X600, NTSC, 7:10 720X576, PAL, 1:1 720X480, NTSC, 1:1 800X500, PAL, 1:1 640X400, NTSC, 1:1
N 10bits
9 110 126 190 647 86 284 94 62 302 31 31 242 2
M 9bits
3 63 63 89 313 33 103 33 19 89 33 33 197 2
Buffered Clock Output Register
Symbol: BCO Address: 17h Bits: 6
5
SHF2 R/W 0
Bit: Symbol: Type: Default:
7
Reserved R/W 0
6
Reserved R/W 1
4
SHF1 R/W 0
3
SHF0 R/W 0
2
SCO2 R/W 0
1
SCO1 R/W 0
0
SCO0 R/W 0
The buffered clock output register determines which clock is selected to be output at the buffered clcok output pin, and what frequency value should be output if a VCO derived signal is output. The tables below show the possible outputs signals.
Table 26.Clock Output Selection
SCO[2:0]
000 001 010 011 100 101 110 111
Buffered Clock Output
14MHz crystal (for test use only) VCO divided by K3 (see Table 27) Field ID signal (for test use only) (for test use only) TV horizontal sync (for test use only) TV vertical sync (for test use only)
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Table 27. K3 Selection
SHF[2:0] 000 001 010 011 100 101 110 111 K3 2.5 3 3.5 4 4.5 5 6 7
CH7013B
Sub-carrier Value Registers
Symbol: FSCI Address: 18h - 1Fh Bits: 4 or 8 each
5
Reserved R/W
Bit: Symbol: Type: Default:
7
Reserved R/W
6
Reserved R/W
4
Reserved R/W
3
FSCI# R/W
2
FSCI# R/W
1
FSCI# R/W
0
FSCI# R/W
The lower four bits of registers 18h through 1Fh contain a 32-bit value which is used as an increment value for the ROM address generation circuitry. The bit locations are specified as the following:
Register 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Contents FSCI[31:28] FSCI[27:24] FSCI[23:20] FSCI[19:16] FSCI[15:12] FSCI[11:8] FSCI[7:4] FSCI[3:0]
When the CH7013B is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21h should be set to "0", and the CFRB bit in register 06h should be set to "1".
Table 28. FSCI Values (525-Line Modes)
Mode 2 3 6 7 10 11 12 16 17 18 22 23 24 26 28 NTSC "Normal Dot Crawl" 763,363,328 623,153,737 574,429,782 463,962,517 646,233,505 516,986,804 452,363,454 623,153,737 545,259,520 508,908,885 521,957,831 469,762,048 428,554,851 569,408,543 1,073,741,824 NTSC "No Dot Crawl" 763,366,524 623,156,346 574,432,187 463,964,459 646,236,211 516,988,968 452,365,347 623,156,346 545,261,803 508,911,016 521,960,016 469,764,015 428,556,645 569,410,927 1,073,746,319 PAL-M "Normal Dot Crawl 762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 516,418,687 451,866,351 622,468,953 544,660,334 508,349,645 521,384,251 469,245,826 428,083,911 568,782,819 1,072,561,888
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Table 29. FSCI Values (625-Line Modes)
Mode 0 1 4 5 8 9 13 14 15 19 20 21 25 27 PAL "Normal Dot Crawl" 806,021,060 644,816,848 601,829,058 485,346,014 677,057,690 537,347,373 806,021,060 644,816,848 537,347,373 645,499,916 528,951,320 488,262,757* 705,268,427 1,073,747,879 PAL-Nc (Argentina) "Normal Dot Crawl" 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 569,807,942 867,513,766
CH7013B
When the CH7013 is operating in the slave clock mode, the ACIV bit in register 21h should be set to "1" and the CFRB bit in register 06h should be set to "0".
*Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0" & ACIV = "0".
PLL Control Register
Symbol: PLLC Address: 20h Bits: 6
6
Reserved R/W 0
Bit: Symbol: Type: Default:
R/W
7
Reserved 0
5
PLLCPI R/W 0 R/W
4
PLLCAP 0 R/W
3
PLLS 1* R/W
2
Reserved 0 R/W
1
PLLVA 1* R/W
0
Reserved 0
The following PLL and memory controls are available through the PLL control register: PLLVA PLLS PLLCAP PLLCPI PLLVA must be set to 0 when the phase-locked loop analog supply is 3.3 volts. The default value of this bit should be overwritten and set to 0. PLLS controls the number of stages used in the PLL and must be changed to 0. When PLLS is set to 0, five stages are used in the PLL.The default value of this bit should be overwritten and set to 0. PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs. Mode is shown below PLLCPI controls the charge pump current of the PLL. The default value should be used.
*Programming
Note: Bit 1 and bit 3 of this register must be programmed to 0.
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Table 30. PLL Capacitor Setting
Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CH7013B
PLLCAP Value
1 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 1
CIV Control Register
Symbol: CIVC Address: 21h Bits: 5
6
Reserved
Bit: Symbol: Type: Default:
7
Reserved
5
Reserved
4
CIV25 R
3
CIV24 R
2
CIVH1 R/W 0
1
CIVH0 R/W 0
0
ACIV R/W 1
The following controls are available through the CIV control register: ACIV When the automatic calculated increment value is 1, the number calculated and present at the CIV registers will automatically be used as the increment value for subcarrier generation, removing the need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to 1, the subcarrier generation must be forced to free-run mode. CIVH[1:0] CIV[25:24] These bits control the hysteresis circuit which is used to calculate the CIV value. See descriptions in the next section.
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Calculated Increment Value Register
CH7013B
Symbol: CIV Address: 22h - 24h Bits: 8
4
CIV# R 0
Bit: Symbol: Type: Default:
7
CIV# R 0
6
CIV# R 0
5
CIV# R 0
3
CIV# R 0
2
CIV# R 0
1
CIV# R 0
0
CIV# R 0
The CIV registers 22h through 24h contain a 26-bit value, which is the calculated increment value that should be used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz clock. The bit locations and calculation of CIV are specified as the following: Register Contents 21h CIV[25:24] 22h CIV[23:16] 23h CIV[15:8] 24h CIV[7:0]
Version ID Register
Symbol: VID Address: 25h Bits: 8
6
VID6 R 0
Bit: Symbol: Type: Default:
7
VID7 R 0
5
VID5 R 1
4
VID4 R 0
3
VID3 R 0
2
VID2 R 0
1
VID1 R 1
0
VID0 R 0
This read-only register contains a 8-bit value indicating the identification number assigned to this version of the CH7013B. The default value shown is pre-programmed into this chip and is useful for checking for the correct version of this chip, before proceeding with its programming.
Address Register
Symbol: AR Address: 3Fh Bits: 6
6
Reserved R/W
Bit: Symbol: Type: Default:
7
Reserved R/W
5
AR5 R/W X
4
AR4 R/W X
3
AR3 R/W X
2
AR2 R/W X
1
AR1 R/W X
0
AR0 R/W X
The Address Register points to the register currently being accessed.
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6. ELECTRICAL SPECIFICATIONS
Table 31. Absolute Maximum Ratings
Symbol Description
VDD relative to GND Input voltage of all digital pins1
CH7013B
Min - 0.5 GND - 0.5
Typ
Max 7.0 VDD + 0.5
Units V V Sec C C C C
TSC TAMB TSTOR TJ TVPS
Analog output short circuit duration Ambient operating temperature Storage temperature Junction temperature Vapor phase soldering (one minute)
Indefinite - 55 - 65 85 150 150 220
Notes: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods my affect reliability. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latch.
2.
Table 32. Recommended Operating Conditions
Symbol VDD AVDD DVDD RL Description
DAC power supply voltage Analog supply voltage Digital supply voltage Output load to DAC outputs
Min
3.15 3.15 3.15
Typ
3.3 3.3 3.3 37.5
Max
3.45 3.45 3.45
Units
V V V
Table 33. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 3.3V, AVDD = 3.3V, DVDD = 3.3V)
Symbol
DAC INL DAC DNL Power Supply Rejection Ratio (AVDD, VDD) Full scale output current Video level error VDD & AVDD (3.3V) current (simultaneous S-Video & composite outputs) DVDD (3.3V) current 100
Description
Video D/A resolution
Min
9 -2 -1
Typ
9
Max
9 5 4
Unit
Bits LSB LSB %FSB/V mA
+/- 24.0 33.9 10
% mA
25
mA
RSET = 300 and NTSC CCIR601 operation.
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CH7013B
Table 34. CH7013B Supply Current Characteristics (AVDD = 3.3V, VDD = 3.3V, DVDD = 3.3V)
Description
Normal Operation IDD1 IDD2 IDD3 IDD1 IDD2 IDD3 IDD1 IDD2 IDD3 Full Power Down IDD Total of DVDD, AVDD, & VDD supply currents 20 uA DVDD supply current AVDD supply current VDD supply current Normal Operation S-Video only DVDD supply current AVDD supply current VDD supply current Normal Operation, composite only DVDD supply current AVDD supply current VDD supply current 25 8 38 mA mA mA 25 8 59 mA mA mA 25 8 92 mA mA mA
Min
Typ
Max
Units
Notes: 1. 2. 3. The above data is typical at 25oC with the following supply voltages: DVDD=3.3V, AVDD=3.3V and VDD=3.3V Current is measured in normal circuit configuration with output loads connected; device operating in mode 17 with POUT at 2X. Actual current will depend on many factors, including operating mode, image content, output clock selections, etc. This table is intended as a general guide only.
Table 35. Digital Inputs/Outputs
Symbol Description
SD (serial port data) Output Low Voltage Serial Port (SC, SD) Input High Voltage Serial Port (SC, SD) Input Low Voltage D[0-15] Input High Voltage D[0-15] Input Low Voltage P-OUT Output High Voltage P-OUT Output Low Voltage IOL = - 400 A IOL = 3.2 mA
Test Condition
IOL = 2.0 mA
Min
Typ
Max
0.4
Unit
V V V V V V
VSDOL VSPIH VSPIL VDATAIH VDATAIL VP-OUTOH VP-OUTOL
2.7 GND - 0.25
DVDDV(1)/2+0.25
DVDDV(1)+0.25
1.4
DVDDV(1)+0.25 DVDDV(1)/2-0.25
GND - 0.25 2.8
0.2
V
Notes: 1. 2. 3. DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. VDATA - refers to all digital pixel and clock inputs. VP-OUT - refers to pixel data output.
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Table 36. Timing - TV Encoder
Symbol
tP1 tPH1 tdc1 tP2 tPH2 tdc2 tP3 tPH3 tdc3
CH7013B
Description Min
20 8 40 10 40 10 40 50 50 50
Typ
50 25 60 25 60 17 60
Max
Unit
ns ns % ns ns % ns ns %
Pixel Clock Period Pixel Clock High Time Pixel Clock Duty Cycle (tPH1/tP1) Pixel Clock Period Pixel Clock High Time Pixel Clock Duty Cycle (tPH2/tP2) Pixel Clock Period Pixel Clock High Time Pixel Clock Duty Cycle (tPH3/tP3)
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7. TIMING INFORMATION
7.1 Clock - Master, Sync - Slave Mode
CH7013B
P-OUT
V OH V OL t2
t1
t1
XCLK XCLK* D[11:0]
V OH V OL V OH V OL t3 V OH P0a V OL t3 t4 P0 b P1a P1 b t4 P2a P2 b t5
H V
V OH V OL V OH V OL 64 PIXELS
1 VGA Line t5 t5
Symbol
VOH VOL t1 t2 t3
Parameter
Output High level of interface signals Output Low level of interface signals P-OUT rise/fall time w/15pF load, VREF
(2)
Min
DVDDV(1)-0.2 -0.2 = 1.65 V 1 1.5
Typ
Max
DVDDV(1)+0.2 0.2
Unit
V V ns
3 3 7
XCLK & XCLK* rise/fall time w/15pF load Setup time: Differential Clock: (XCLK = XCLK*) to (D[11:0], H, & V) Single-ended Clock: (XCLK =VREF(2)) to (D[11:0], H, & V) Hold time: Differential Clock: (XCLK = XCLK*) to (D[11:0], H, & V) Single-ended Clock: (XCLK =VREF(2)) to (D[11:0], H, & V) D[11:0], H, & V rise/fall time w/15pF load
ns ns
t4 t5
1.5
ns
3
ns
Notes: 1. 2. DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. VREF: I/O Reference voltage. In general cases, VREF = DVDDV/2.
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7.2 Clock - Master, Sync - Master Mode
CH7013B
P-OUT H V
VOH VOL VOH VOL VOH VOL t5 1 VGA Line t5 t2 t6 t7 64 PIXELS
t1
t1
XCLK XCLK* D[11:0]
VOH VOL VOH VOL t3 VOH P0a VOL P0b P1a P1b P2a P2b t5 t4
Symbol
VOH VOL t1 t2 t3
Parameter
Output High level of interface signals Output Low level of interface signals P-OUT rise/fall time w/15pF load, VREF(2) = 1.65 V XCLK & XCLK* rise/fall time w/15pF load Setup time: Differential Clock: (XCLK = XCLK*) to (D[11:0], H, & V = VREF(2)) Single-ended Clock: (XCLK =VREF) to (D[11:0], H, & V = VREF(2)) Hold time: Differential Clock: (XCLK = XCLK*) to (D[11:0], H, & V = VREF(2)) Single-ended Clock: (XCLK =VREF) to (D[11:0], H, & V = VREF(2)) D[11:0], H, & VS rise/fall time w/15pF load Hold time: P-OUT to HSYNC, VSYNC delay (P-OUT=VREF(2)) to (XCLK =XCLK*) delay
Min
DVDDV -0.2 -0.2
(1)
Typ
Max
DVDDV +0.2 0.2
(1)
Unit
V V ns
3 1 1.5 3 7
ns ns
t4 t5 t6 t7
1.5
ns
3 1 2 1.5 2.5 9
ns ns ns
Notes: 1. 2. DVDDV : Digital I/O Supply Voltage. The typical value is +3.3V. VREF: I/O Reference voltage. In general cases, VREF = DVDDV/2.
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8. PACKAGE DIMENSIONS
8.1 48-pin LQFP (7mm x 7mm)
CH7013B
A B I
1
A
B
H
C
D
J
F G
LEAD CO-PLANARITY
E
.004 "
Table of Dimensions
No. of Leads 48 (7 X 7 mm)
SYMBOL A 8.80 9.20 B - 7 C 0.50 D 0.17 0.27 E 1.35 1.45 F 0.05 0.15 G 1.00 H 0.45 0.75 I 0.09 0.20 J 0 7
Millimeters
MIN MAX
Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D. 2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
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9. REVISION HISTORY
Rev. #
1.0 1.1 1.2
CH7013B
Section
All 6 5&6
Date
5/25/04 7/12/04 9/1/04
Description
First official release of CH7013B datasheet, rev. 1.0 Power down currents updated Supported modes updated. Current consumption updated
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Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part number CH7013B-D CH7013B-D-TR CH7013B-DF CH7013B-DF-TR Package type LQFP LQFP, Tape&Reel LQFP, Lead free LQFP, Lead free, Tape&Reel Number of pins 48 48 48 48 Voltage supply 3.3V 3.3V 3.3V 3.3V
Chrontel
2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
(c)2004 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A.
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